1. Field of the Invention
The present invention relates to encoding for disk drives and, particularly, to an improved Viterbi trellis for sampled amplitude read channels.
2. Description of the Related Art
In order to achieve higher recording densities and reduce intersymbol interference, designers of magnetic recording channels have switched from analog peak detection techniques to sampled data detection techniques. In sampled data detection systems, the readback signal is filtered and sampled at a channel rate of 1/T, where T is the duration of a channel symbol.
One such technique is referred to as xe2x80x9cpartial response with maximum likelihoodxe2x80x9d (PRML). In PRML systems, the output of the noisy partial response channel is sampled at the channel rate and detected using a maximum likelihood Viterbi detector.
The partial response channel has a transfer function of the form (1xe2x88x92D)(1+D) or 1xe2x88x92D2, where D represents a unit time delay operator with unit-time T. Thus, the noiseless output of the partial response channel is equal to the input signal minus a version of the input delayed in time by period 2T.
To further increase recording density and decrease the need for equalization, higher order PRML systems have been developed. The extended partial response with maximum likelihood (EPRML) channel has a transfer function of the form (1xe2x88x92D)(1+D)2 or (1+Dxe2x88x92D2xe2x88x92D3). Thus, the noiseless output of the extended partial response channel is equal to the input signal minus a version of the input signal delayed in time by 2T, minus a version of the input signal delayed in time by 3T and plus a version of the input signal delayed in time by T. Similarly, the E2PRML channel has a transfer function of the form (1xe2x88x92D)(1+D)3.
As noted above, Viterbi decoders are typically employed in sampled amplitude channels. Viterbi decoders are specific implementations of the Viterbi algorithm. A Viterbi detector unit is based on periodic examination of metrics associated with alternate sequences of recorded bits, wherein each sequence is typically labeled as a xe2x80x9cpathxe2x80x9d and the associated metric is designated a xe2x80x9cpath metric.xe2x80x9d The most probable correct path is then determined by choosing a minimum path metric based on an iterative process involving successive comparison of associated path metrics.
In particular, two paths within a constrained, predetermined path length are examined. Since the recorded bit only depends on the constraint length corresponding to a finite number of neighbor bits, it becomes possible to abandon the path associated with the larger of the two path metrics corresponding to each path pair. Consequently, the number of possible paths can be restricted to a finite value by abandoning all but one of the total number of paths each time a new bit is added and examined during the data detection procedure. This process of path abandonment in order to compute the best path to each node of the trellis is executed by a sequence of operations commonly referred to as add-compare-select or ACS.
In many instances of implementing sampled amplitude channels, for example, it is desirable to implement a system of more than one partial response channel type. Conventionally, this has required implementation of unique trellises for each type. This is disadvantageous in that implementation costs are relatively increased. Further, implementing multiple partial response channel types each with its own trellis on a single integrated circuit chip can require different amounts of chip space, which can result in sub-optimal chip space usage.
These and other drawbacks in the prior art are overcome in large part by a system and method according to the present invention. In particular, the present invention allows for implementation of either an EPRML type channel or an E2PRML type channel using a single trellis structure. According to one implementation, a trellis is provided which can support a 0 mod 2 (i.e., there are an even number of 1""s in every codeword) EPRML (M2EPRML) channel and a modified E2PRML (ME2PRML) channel.
According to one implementation, a sixteen-state trellis is provided. Sixteen of thirty-two edges in the M2EPRML carry the same non-return-to-zero (NRZ) values as the corresponding edges of the ME2PRML trellis, and sixteen of thirty-two edges carry the same sample values. The trellis supports M2EPRML if sixteen of its edges are eliminated every P clock cycles, where P is the block length of the code. The trellis can support ME2PRML sequences if four of its edges are eliminated every k mod 9 (k in {1, 2, 4, 6, 8}) clock cycles.
A better understanding of the invention is obtained when the following detailed description is considered in conjunction with the following drawings.